Commit graph

212767 commits

Author SHA1 Message Date
Android Build Coastguard Worker
f0981471e9 Snap for 14019536 from 596b781dc2 to 25Q4-release
Change-Id: Ie0610a22cb2bfedbb262f5e75992505d233adb3d
2025-08-29 18:39:02 -07:00
Serdar Kocdemir
596b781dc2 Merge "Enable VK_MVK_macos_surface for host dispatch" into main 2025-08-29 09:12:09 -07:00
Serdar Kocdemir
f3af075b34 Enable VK_MVK_macos_surface for host dispatch
To be used in Vulkan composition on macOS.

Bug: 389646068
Test: -feature GuestAngle, VulkanNativeSwapchain
Change-Id: I7f7d67b56f89277da1ed61852c96b99dc0cce26d
2025-08-26 15:31:50 +01:00
Android Build Coastguard Worker
1a6ddadd9e Snap for 13989311 from ee57f856c8 to 25Q4-release
Change-Id: Ifd907c3c04aa7e56a32cb701f75a4918cddd29b9
2025-08-25 16:51:44 -07:00
Android Build Coastguard Worker
1e6761549c Snap for 13982012 from 445f0731c2 to 25Q4-release
Change-Id: I78f62d7d089d06e5998117423bdec52c9867536c
2025-08-22 18:15:26 -07:00
Jason Macnak
ee57f856c8 Enable perfetto in mesa targets
Bug: b/440065361
Test: Capture guest and host trace and inspect in perfetto UI
Change-Id: Icad207776552f5b06398ee58872cfe85ef4eb2fc
2025-08-22 20:35:44 +00:00
Matt Turner
e75c61c62d UPSTREAM: meson: Allow configuring with Android-internal perfetto
This enables ninja-to-soong to generate an Android.bp that builds Mesa
against Android's `libperfetto_client_experimental` library.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36561>
Change-Id: I14f43cfeb6e163fb0de7098b0131541a0df05109
2025-08-22 20:20:57 +00:00
Matt Turner
0526c2ae77 UPSTREAM: meson: Allow controlling perfetto fallback
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36561>
Change-Id: Iacf85a6d70f65910af109d61ad18e333f1fea663
2025-08-22 20:20:51 +00:00
Android Build Coastguard Worker
d28630a384 Snap for 13972532 from d4c765611b to 25Q4-release
Change-Id: I3a44bb3ef202b6b857a63525a67d9e3b2b87f334
2025-08-21 16:32:21 -07:00
Jason Macnak
445f0731c2 Hide vkTraceAsyncGOOGLE behind new capset flag
... to make it forward compatible / to make it not crash older
Gfxstream host builds.

Bug: b/440065361
Test: Capture guest and host trace and inspect in perfetto UI
Change-Id: I5f0d0618f208de5728c21eb72cfee8112e535e64
2025-08-21 19:38:02 +00:00
Jason Macnak
d4c765611b Add a vkTraceAsyncGOOGLE
... to allow sharing perfetto global flow ids between guest and host
so that combined traces can have an arrow between the guest and host
render threads to aid debugging.

Bug: b/440065361
Test: Capture guest and host trace and inspect in perfetto UI
Change-Id: Ib4ce85fd48cf20d06ff88d8cda54fb4143e28569
2025-08-20 20:10:39 +00:00
Android Build Coastguard Worker
486e181aba Snap for 13937020 from a110af6a34 to 25Q4-release
Change-Id: If9b975f9dbd548bdda51580b0fae9286740738d4
2025-08-14 16:20:57 -07:00
sergiuferentz
a110af6a34 VirtGpuDevice can be null for Goldfish.
Test: atest CtsDeqpTestCases -- --module-arg 'CtsDeqpTestCases:include-filter:dEQP-VK.image.swapchain_mutable.android.2d*'
Bug: 438487556
Change-Id: I4a740fbb223e0987a1d0b86f7efe47f09267b65b
2025-08-14 15:14:04 +01:00
Android Build Coastguard Worker
9bb13d585d Snap for 13921250 from 055a8b5a05 to 25Q4-release
Change-Id: I7dc744cefdab9fde24c6f969240148c4c541a4a6
2025-08-12 16:13:18 -07:00
Bo Hu
055a8b5a05 [vulkan snapshot]: update code gen for vkUpdateDescriptorSet change
Bug: 417788798

Change-Id: I2d90247125efc152855c25f620428a100c98eb04
2025-08-05 22:34:57 -07:00
Android Build Coastguard Worker
b694085090 Snap for 13886633 from 648199ae76 to 25Q4-release
Change-Id: I9920f7e0157af248d199dfe4b2329c579a6b7db3
2025-08-05 16:13:48 -07:00
Gurchetan Singh
648199ae76 Merge remote-tracking branch 'goog/upstream-main' into HEAD
Mesa merge, August 1 2025.

BUG=none
TEST=CI/CD

Change-Id: I8fb9e42a6bcda66a342e512b953deb5454e58385
2025-08-01 14:05:32 -07:00
Georg Lehmann
cfd5fbfde1 nir/opt_algebraic: make fmin/fmax(a, #b) 16bit if only used by f2f16
Foz-DB Navi31:
Totals from 11 out of 14 FSR4 shaders:
Instrs: 58298 -> 58374 (+0.13%); split: -0.08%, +0.21%
CodeSize: 397836 -> 398108 (+0.07%); split: -0.08%, +0.15%
Latency: 209634 -> 211438 (+0.86%); split: -0.14%, +1.00%
InvThroughput: 229152 -> 229314 (+0.07%); split: -0.03%, +0.10%
VClause: 826 -> 847 (+2.54%); split: -0.36%, +2.91%
Copies: 2954 -> 3040 (+2.91%); split: -1.56%, +4.47%
VALU: 49637 -> 49711 (+0.15%); split: -0.06%, +0.21%
VOPD: 1916 -> 1400 (-26.93%)

These stats looks bad, but it's actually just unlucky RA.
Replacing 1 VOPD (two v_dual_max_f32) with 1 VOP3P (v_pk_max_f16)
should still be a win from a register bandwidth perspective.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36468>
2025-08-01 20:29:30 +00:00
Georg Lehmann
3168ebe2c5 nir/range_analysis: look through vec2
Foz-DB Navi31:
Totals from 11 out of 14 FSR4 shaders:
Instrs: 58987 -> 58298 (-1.17%)
CodeSize: 402844 -> 397836 (-1.24%)
Latency: 209630 -> 209634 (+0.00%); split: -0.66%, +0.66%
InvThroughput: 230240 -> 229152 (-0.47%); split: -0.48%, +0.00%
VClause: 838 -> 826 (-1.43%); split: -1.55%, +0.12%
Copies: 3019 -> 2954 (-2.15%); split: -2.82%, +0.66%
VALU: 50196 -> 49637 (-1.11%)
VOPD: 1950 -> 1916 (-1.74%); split: +0.72%, -2.46%

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36468>
2025-08-01 20:29:29 +00:00
Georg Lehmann
caf89c97de nir/range_analysis: look through f2f
Foz-DB Navi31:
Totals from 93 (0.12% of 80273) affected shaders:
Instrs: 123927 -> 121073 (-2.30%); split: -2.30%, +0.00%
CodeSize: 670832 -> 653332 (-2.61%); split: -2.61%, +0.00%
Latency: 337678 -> 322803 (-4.41%); split: -4.41%, +0.00%
InvThroughput: 63277 -> 61083 (-3.47%)
VClause: 460 -> 373 (-18.91%)
SClause: 2178 -> 2100 (-3.58%)
Copies: 7637 -> 7744 (+1.40%)
PreSGPRs: 4414 -> 4287 (-2.88%)
PreVGPRs: 4229 -> 4230 (+0.02%)
VALU: 77375 -> 75693 (-2.17%)
SALU: 16497 -> 16383 (-0.69%); split: -0.73%, +0.04%
VMEM: 561 -> 477 (-14.97%)
SMEM: 3197 -> 3113 (-2.63%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36468>
2025-08-01 20:29:28 +00:00
Georg Lehmann
261239a492 nir/opt_algebraic: use range analysis to detect no-op fmin/fmax
Foz-DB Navi31:
Totals from 418 (0.52% of 80273) affected shaders:
Instrs: 564550 -> 564387 (-0.03%); split: -0.04%, +0.01%
CodeSize: 2983860 -> 2982684 (-0.04%); split: -0.05%, +0.01%
Latency: 4387264 -> 4386397 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 717464 -> 716874 (-0.08%); split: -0.08%, +0.00%
Copies: 40126 -> 40125 (-0.00%)
VALU: 352128 -> 352003 (-0.04%); split: -0.04%, +0.01%
SALU: 50290 -> 50283 (-0.01%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36468>
2025-08-01 20:29:28 +00:00
Georg Lehmann
a0665e79e9 nir/opt_algebraic: push fsat into bcsel with constant
bcsel doesn't have a free clamp modifier on AMD hardware,
but what's inside might have free clamp.

Foz-DB Navi31:
Totals from 873 (1.09% of 80273) affected shaders:
MaxWaves: 22008 -> 21968 (-0.18%)
Instrs: 4624956 -> 4623950 (-0.02%); split: -0.04%, +0.02%
CodeSize: 24152780 -> 24142884 (-0.04%); split: -0.05%, +0.01%
VGPRs: 57900 -> 57960 (+0.10%)
Latency: 28762622 -> 28749889 (-0.04%); split: -0.06%, +0.02%
InvThroughput: 5320810 -> 5320145 (-0.01%); split: -0.02%, +0.00%
VClause: 115879 -> 115929 (+0.04%); split: -0.10%, +0.14%
SClause: 93058 -> 93059 (+0.00%); split: -0.01%, +0.02%
Copies: 335674 -> 335845 (+0.05%); split: -0.05%, +0.10%
PreSGPRs: 53819 -> 53843 (+0.04%); split: -0.01%, +0.05%
PreVGPRs: 50908 -> 50939 (+0.06%); split: -0.02%, +0.08%
VALU: 2816395 -> 2815514 (-0.03%); split: -0.04%, +0.01%
SALU: 509988 -> 509987 (-0.00%); split: -0.02%, +0.02%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36468>
2025-08-01 20:29:27 +00:00
Georg Lehmann
e9e5146848 nir/opt_algebraic: optimize fsat(fmax(a, b)) where b is not positive
Foz-DB Navi31:
Totals from 946 (1.18% of 80273) affected shaders:
Instrs: 4986082 -> 4983988 (-0.04%); split: -0.04%, +0.00%
CodeSize: 25998700 -> 25989796 (-0.03%); split: -0.04%, +0.00%
Latency: 45514742 -> 45510330 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 8163529 -> 8162325 (-0.01%); split: -0.02%, +0.00%
VClause: 112105 -> 112104 (-0.00%); split: -0.00%, +0.00%
SClause: 109694 -> 109688 (-0.01%)
Copies: 372356 -> 372284 (-0.02%); split: -0.03%, +0.01%
Branches: 132636 -> 132633 (-0.00%)
PreVGPRs: 58997 -> 58979 (-0.03%); split: -0.03%, +0.00%
VALU: 3025662 -> 3024191 (-0.05%); split: -0.05%, +0.00%
SALU: 551712 -> 551714 (+0.00%); split: -0.00%, +0.00%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36468>
2025-08-01 20:29:27 +00:00
Rob Clark
898fa317dd util: Optimize MESA_TRACE_FUNC()
Avoiding the vsnprintf speeds up drawoverhead -test 3 by 60+% !!

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36492>
2025-08-01 19:58:24 +00:00
Rob Clark
b833bb2df4 freedreno/registers: Fix DBGC_CFG_DBGBUS_SEL_D definition
Offset is the same, but bitfields change between a6xx and a7xx.  Syncing
the change from https://patchwork.freedesktop.org/series/152200/

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36426>
2025-08-01 19:33:28 +00:00
Rob Clark
a05b6e293c freedreno/crashdec: Add option to export a snapshot
Add support to convert into the "snapshot" format used by internal
tooling.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36426>
2025-08-01 19:33:28 +00:00
Rob Clark
08b9d771e3 freedreno/crashdec: Sanitize index-regs section names
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36426>
2025-08-01 19:33:28 +00:00
Rob Clark
d8840db682 freedreno/decode: Add enum value decoding
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36426>
2025-08-01 19:33:27 +00:00
Job Noorman
c8f9990733 ir3/legalize: prevent infinite loop when inserting (ss)nop
We need to insert a (ss)nop when an instruction that doesn't support
(ss) needs it. However, when this happens in a block that needs to be
legalized more than once (e.g., because it is in a loop), the (ss)nop
would be inserted every iteration, causing an infinite loop.

Fix this by checking if the previous instructions is a nop and applying
(ss) there.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 5993723471 ("freedreno/a3xx/compiler: scheduling/legalize fixes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36440>
2025-08-01 19:08:23 +00:00
Paulo Zanoni
257e1515e3 brw: null-tile sends don't need to skip L3 on Xe2 and newer
Despite the information in "Overview of Memory Access" (57046), the L3
seems to be smarter on Xe2+. See 4aa3b2d3ad ("anv: LNL+ doesn't need
the special flush for sparse").

The behavior is the same both with vm_bind and TR-TT.

v2: Add some comments (Caio).

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
2025-08-01 18:47:37 +00:00
Paulo Zanoni
80f01c03ba brw: remove unnecessary casts to unsigned after calling LSC_CACHE()
The macro already casts the values to unsigned.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
2025-08-01 18:47:37 +00:00
Paulo Zanoni
c845b30a21 brw: adjust comment pasted from a commit message
The comment was pasted from the commit message that added it. Remove
the parts that only make sense in the commit message, not in the final
code.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
2025-08-01 18:47:37 +00:00
Paulo Zanoni
4bb41156b9 brw: mark 'volatile' sends as uncached on LSC messages
The residencyNonResidentStrict property requires that writes to
unbound memory be ignored and reads return zero. We need this
property, otherwise vkd3d will claim we don't support DX12.

If a shader writes to a variable associated with an unbound memory
region (i.e., mapped to a null tile), reads it back (in the same
shader) and expects the value be 0 instead of what is wrote, it has to
use the 'volatile' access qualifier to the variable associated with
the access, otherwise the compiler will be allowed to optmize things
and use the non-zero value.  This is explained in the "Accessing
Unbound Regions" section of the Vulkan spec.

Our hardware adds an extra problem on top of the above. BSpec page
"Overview of Memory Access" (47630, 57046) says:

  "If a read from a Null tile gets a cache-hit in a
   virtually-addressed GPU cache, then the read may not return
   zeroes."

So, when we detect this type of access, we have to turn off the
caching.

There's a proposed Vulkan CTS test that does exactly the above.

No shaders on shader_db seem to be using 'volatile'.

v2:
 - Reorder commit order
 - Rewrite commit message

v3:
 - Rework the patch after Caio pointed out the interaction with
   'coherent'.
 - Remove previous R-B tags due to the patch differences.

v4:
 - Rework the patch and commit message again after further
   discussions.

v5:
 - Check for atomic first so we don't regress DG2 atomic tests.

Fixes future test: dEQP-VK.sparse_resources.buffer.ssbo.read_write.sparse_residency_non_resident_strict

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
2025-08-01 18:47:37 +00:00
Paulo Zanoni
f7581e4a38 brw: consider 'volatile' memory access when doing CSE
The GLSL spec says (among other things):

  "When a volatile variable is read, its value must be re-fetched from
   the underlying memory, even if the shader invocation performing the
   read had previously fetched its value from the same memory. When a
   volatile variable is written, its value must be written to the
   underlying memory, even if the compiler can conclusively determine
   that its value will be overwritten by a subsequent write."

The SPIR-V spec says (among other things):

  "Accesses to volatile memory cannot be eliminated, duplicated, or
   combined with other accesses."

So in this commit we make sure that both writes and reads marked as
volatile can't be affected by CSE.

v2: Reorder patches in the series.

Credits-to: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Iván Briano <ivan.briano@intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
2025-08-01 18:47:36 +00:00
Paulo Zanoni
8e1e3ba152 brw: store 'volatile' GLSL/SPIR-V access in MEMORY_LOGICAL_FLAGS
We seem to be ignoring the 'volatile' keyword coming from the shaders.
Record this in MEMORY_LOGICAL_FLAGS so we can use it later.

Credits-to: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
2025-08-01 18:47:36 +00:00
Paulo Zanoni
670cd08c68 brw: remove unnecessary <vector> inclusions
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36150>
2025-08-01 18:47:35 +00:00
Jeongik Cha
3e39c09aa0 gfxstream: Generate goldfish dispatch code for AHB extension
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36510>
2025-08-01 18:34:15 +00:00
Daniel Schürmann
4ca3cc5a1a aco/ra: propagate precolor affinities through parallelcopies and tied definitions
Totals from 214 (0.27% of 79839) affected shaders: (Navi48)

Instrs: 65339 -> 65311 (-0.04%); split: -0.05%, +0.00%
CodeSize: 352616 -> 350952 (-0.47%); split: -0.55%, +0.07%
VGPRs: 9984 -> 9960 (-0.24%)
Latency: 207556 -> 207508 (-0.02%); split: -0.03%, +0.01%
InvThroughput: 40422 -> 40397 (-0.06%)
Copies: 3180 -> 3155 (-0.79%)
VALU: 38347 -> 38322 (-0.07%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
a667d9a68d aco/ra: propagate precolor affinities through phis
Totals from 917 (1.15% of 79839) affected shaders: (Navi48)

Instrs: 3217861 -> 3216947 (-0.03%); split: -0.04%, +0.01%
CodeSize: 17427204 -> 17432264 (+0.03%); split: -0.06%, +0.09%
VGPRs: 65328 -> 65316 (-0.02%)
Latency: 35336268 -> 35335528 (-0.00%); split: -0.01%, +0.01%
InvThroughput: 7305032 -> 7302187 (-0.04%); split: -0.04%, +0.00%
SClause: 120537 -> 120553 (+0.01%); split: -0.01%, +0.02%
Copies: 307257 -> 306852 (-0.13%); split: -0.21%, +0.08%
Branches: 115744 -> 115743 (-0.00%)
VALU: 1572522 -> 1572183 (-0.02%); split: -0.02%, +0.00%
SALU: 574229 -> 574155 (-0.01%); split: -0.05%, +0.04%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
2ddd8ef0a3 aco/ra: don't optimize encodings on precolor affinity mismatch
Totals from 238 (0.30% of 79839) affected shaders: (Navi48)
Instrs: 137836 -> 137176 (-0.48%); split: -0.50%, +0.02%
CodeSize: 728616 -> 728668 (+0.01%); split: -0.06%, +0.07%
Latency: 1503248 -> 1500202 (-0.20%); split: -0.56%, +0.36%
InvThroughput: 297725 -> 296715 (-0.34%); split: -0.70%, +0.36%
Copies: 9390 -> 8825 (-6.02%); split: -6.33%, +0.31%
VALU: 89861 -> 89296 (-0.63%); split: -0.66%, +0.03%
SALU: 13166 -> 13167 (+0.01%); split: -0.05%, +0.06%

Suggested-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
93606a19c6 aco/ra: collect register affinities for all precolored operands.
Totals from 1280 (1.60% of 79839) affected shaders: (Navi48)

Instrs: 817363 -> 812639 (-0.58%); split: -0.58%, +0.00%
CodeSize: 4262644 -> 4243540 (-0.45%); split: -0.45%, +0.00%
VGPRs: 61692 -> 61668 (-0.04%)
Latency: 4354318 -> 4347818 (-0.15%); split: -0.15%, +0.00%
InvThroughput: 711914 -> 707698 (-0.59%); split: -0.59%, +0.00%
VClause: 14685 -> 14677 (-0.05%); split: -0.09%, +0.03%
SClause: 25623 -> 25621 (-0.01%)
Copies: 50663 -> 46242 (-8.73%); split: -8.73%, +0.00%
VALU: 427744 -> 423323 (-1.03%); split: -1.03%, +0.00%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
e32eec52f0 aco/ra: generalize register affinities
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Daniel Schürmann
caa2c22d8b aco/tests: Fix p_startpgm definitions to registers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36345>
2025-08-01 17:15:54 +00:00
Mike Blumenkrantz
779ea64c7c mesa: fix and advertise GL_EXT_sRGB
Co-authored-by: Juan A. Suárez <jasuarez@igalia.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36178>
2025-08-01 16:28:24 +00:00
Mike Blumenkrantz
d32c2b7c24 zink: add cezanne skip for a device loss flake
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36520>
2025-08-01 16:08:48 +00:00
Alyssa Rosenzweig
5761213587 asahi: clang-format
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
2025-08-01 15:34:24 +00:00
Alyssa Rosenzweig
bcf1a1c20b treewide: use nir_def_block
Via Coccinelle patch:

    @@
    expression definition;
    @@

    -definition->parent_instr->block
    +nir_def_block(definition)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
2025-08-01 15:34:24 +00:00
Alyssa Rosenzweig
82ae8b1d33 treewide: simplify nir_def_rewrite_uses_after
Most of the time with nir_def_rewrite_uses_after, you want to rewrite after the
replacement. Make that the default thing to be more ergonomic and to drop
parent_instr uses.

We leave nir_def_rewrite_uses_after_instr defined if you really want the old
signature with an arbitrary after point.

Via Coccinelle patch:

    @@
    expression a, b;
    @@

    -nir_def_rewrite_uses_after(a, b, b->parent_instr)
    +nir_def_rewrite_uses_after_def(a, b)

Followed by a bunch of sed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
2025-08-01 15:34:24 +00:00
Alyssa Rosenzweig
cc6e3b84cb treewide: use nir_def_as_*
Via Coccinelle patch:

    @@
    expression definition;
    @@

    -nir_instr_as_alu(definition->parent_instr)
    +nir_def_as_alu(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_intrinsic(definition->parent_instr)
    +nir_def_as_intrinsic(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_phi(definition->parent_instr)
    +nir_def_as_phi(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_load_const(definition->parent_instr)
    +nir_def_as_load_const(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_deref(definition->parent_instr)
    +nir_def_as_deref(definition)

    @@
    expression definition;
    @@

    -nir_instr_as_tex(definition->parent_instr)
    +nir_def_as_tex(definition)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
2025-08-01 15:34:24 +00:00
Alyssa Rosenzweig
114bf69956 nir: add nir_def_block helper
Another common composition.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36489>
2025-08-01 15:34:24 +00:00