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[PATCH v4 1/3] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up()

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Date: Thu, 17 Apr 2025 08:35:09 +0800	[thread overview]
Message-ID: <1744850111-236269-1-git-send-email-shawn.lin@rock-chips.com> (raw)

Two mistakes here:
1. 0x11 is L0 not L0S, so the naming is wrong from the very beginning.
2. It's totally broken if enabling ASPM as rockchip_pcie_link_up() treat
other states, for instance, L0S or L1 as link down which is obviously
wrong.

Remove the check.

Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Niklas Cassel <cassel@kernel.org>
This commit is contained in:
dvab-sarma 2025-12-11 03:53:20 -06:00
parent 2a84642e99
commit 8b7d53a27b
1 changed files with 4 additions and 3 deletions
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7
drivers/pci/controller/dwc/pcie-dw-rockchip.c
View file

@ -44,7 +44,7 @@
#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
#define PCIE_RDLH_LINK_UP_CHGED BIT(1)
#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)
#define PCIE_L0S_ENTRY 0x11
//#define PCIE_L0S_ENTRY 0x11
#define PCIE_CLIENT_GENERAL_CONTROL 0x0
#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
@ -177,8 +177,9 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci)
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
u32 val = rockchip_pcie_get_ltssm(rockchip);
if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
(val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
// if ((val & PCIE_LINKUP) == PCIE_LINKUP &&
// (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)
if((val & PCIE_LINKUP) == PCIE_LINKUP)
return 1;
return 0;