lineage-rockchip/android_kernel_rockchip_tart
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These changes enable the dp0 node of rk3588(s), which enables DisplayPort of the SoC. This is essential as the seconday hdmi port of Orange pi 5 pro is fundamentally a DP port

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with dp to hdmi converter bridge present. By enabling this, we can use the 2nd hdmi as a secondary display for AOSP(or even primary if first hdmi port is not used).
This commit is contained in:
dvab-sarma 2025-12-04 02:12:24 -06:00
parent 2b492fc2fd
commit 4176d76292
24 changed files with 2898 additions and 43 deletions
Download patch file Download diff file Expand all files Collapse all files

108
arch/arm64/boot/dts/rockchip/overlays/orangepi-pro-cam1.dts Normal file
View file

@ -0,0 +1,108 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&csi2_dphy0_hw>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&csi2_dphy0>;
__overlay__ {
status = "okay";
};
};
fragment@2 {
target = <&mipi2_csi2>;
__overlay__ {
status = "okay";
};
};
fragment@3 {
target = <&rkcif_mipi_lvds2>;
__overlay__ {
status = "okay";
};
};
fragment@4 {
target = <&rkcif_mipi_lvds2_sditf>;
__overlay__ {
status = "okay";
};
};
fragment@5 {
target = <&rkisp0_vir1>;
__overlay__ {
status = "okay";
};
};
fragment@6 {
target = <&i2c7>;
__overlay__ {
status = "okay";
// vm149c-p1@c {
// status = "okay";
// };
// ov13850-1@10 {
// status = "okay";
// };
// dw9714-p1@c {
// status = "okay";
// };
ov13855-1@36 {
status = "okay";
};
};
};
fragment@7 {
target = <&rkcif>;
__overlay__ {
status = "okay";
};
};
fragment@8 {
target = <&rkcif_mmu>;
__overlay__ {
status = "okay";
};
};
fragment@9 {
target = <&rkisp0>;
__overlay__ {
status = "okay";
};
};
fragment@10 {
target = <&isp0_mmu>;
__overlay__ {
status = "okay";
};
};
};

6
arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi
View file

@ -616,7 +616,10 @@
};
&usb_host0_xhci {
dr_mode = "host";
// dr_mode = "host";
phys = <&usb2phy0_otg>;
phy-names = "usb2-phy";
dr_mode = "otg";
status = "okay";
};
@ -629,6 +632,7 @@
};
&usb_host1_xhci {
dr_mode = "otg";
status = "okay";
};

60
arch/arm64/boot/dts/rockchip/rk3588-base-2.dtsi
View file

@ -1396,6 +1396,21 @@
status = "disabled";
};
spdif_tx2: spdif-tx@fddb0000 {
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
reg = <0x0 0xfddb0000 0x0 0x1000>;
assigned-clock-parents = <&cru PLL_AUPLL>;
assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>;
dma-names = "tx";
dmas = <&dmac1 6>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&power RK3588_PD_VO0>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s4_8ch: i2s@fddc0000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc0000 0x0 0x1000>;
@ -1503,6 +1518,42 @@
};
};
dp0: dp@fde50000 {
compatible = "rockchip,rk3588-dp";
reg = <0x0 0xfde50000 0x0 0x4000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
<&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>,
<&cru MCLK_SPDIF2_DP0>;
clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
assigned-clocks = <&cru CLK_AUX16M_0>;
assigned-clock-rates = <16000000>;
resets = <&cru SRST_DP0>;
phys = <&usbdp_phy0 PHY_TYPE_DP>;
//phys = <&usbdp_phy0_dp>;
power-domains = <&power RK3588_PD_VO0>;
#sound-dai-cells = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
dp0_in: port@0 {
reg = <0>;
};
dp0_out: port@1 {
reg = <1>;
};
// port@1 {
// reg = <1>;
// dp0_out: endpoint { };
// };
};
};
hdmi0: hdmi@fde80000 {
compatible = "rockchip,rk3588-dw-hdmi-qp";
reg = <0x0 0xfde80000 0x0 0x20000>;
@ -2984,6 +3035,15 @@
rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
// usbdp_phy0_dp: dp-port {
// #phy-cells = <0>;
// status = "okay";
// };
// usbdp_phy0_u3: u3-port {
// #phy-cells = <0>;
// status = "disabled";
// };
};
mipidcphy0: phy@feda0000 {

20
arch/arm64/boot/dts/rockchip/rk3588-base-3.dtsi
View file

@ -1158,16 +1158,16 @@
};
};
vpu121: video-codec@fdb50000 {
compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
reg = <0x0 0xfdb50000 0x0 0x800>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vdpu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "hclk";
iommus = <&vpu121_mmu>;
power-domains = <&power RK3588_PD_VDPU>;
};
// vpu121: video-codec@fdb50000 {
// compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
// reg = <0x0 0xfdb50000 0x0 0x800>;
// interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
// interrupt-names = "vdpu";
// clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
// clock-names = "aclk", "hclk";
// iommus = <&vpu121_mmu>;
// power-domains = <&power RK3588_PD_VDPU>;
// };
vpu121_mmu: iommu@fdb50800 {
compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";

70
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
View file

@ -1248,6 +1248,66 @@
#iommu-cells = <0>;
};
vdec0: video-codec@fdc38000 {
compatible = "rockchip,rk3588-vdec";
reg = <0x0 0xfdc38000 0x0 0x100>, <0x0 0xfdc38100 0x0 0x500>, <0x0 0xfdc38600 0x0 0x100>;
reg-names = "link", "function", "cache";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
<&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
<&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
assigned-clock-rates = <800000000>, <600000000>,
<600000000>, <1000000000>;
//iommus = <&vdec0_mmu>;
resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
<&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
power-domains = <&power RK3588_PD_RKVDEC0>;
sram = <&vdec0_sram>;
};
vdec0_mmu: iommu@fdc38700 {
compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
clock-names = "aclk", "iface";
power-domains = <&power RK3588_PD_RKVDEC0>;
#iommu-cells = <0>;
status = "disabled";
};
vdec1: video-codec@fdc40000 {
compatible = "rockchip,rk3588-vdec";
reg = <0x0 0xfdc40000 0x0 0x100>, <0x0 0xfdc40100 0x0 0x500>, <0x0 0xfdc40600 0x0 0x100>;
reg-names = "link", "function", "cache";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
<&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
<&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
assigned-clock-rates = <800000000>, <600000000>,
<600000000>, <1000000000>;
resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
<&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
//iommus = <&vdec1_mmu>;
power-domains = <&power RK3588_PD_RKVDEC1>;
sram = <&vdec1_sram>;
};
vdec1_mmu: iommu@fdc40700 {
compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
clock-names = "aclk", "iface";
power-domains = <&power RK3588_PD_RKVDEC1>;
#iommu-cells = <0>;
status = "disabled";
};
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
@ -2973,6 +3033,16 @@
ranges = <0x0 0x0 0xff001000 0xef000>;
#address-cells = <1>;
#size-cells = <1>;
vdec0_sram: codec-sram@0 {
reg = <0x0 0x78000>;
pool;
};
vdec1_sram: codec-sram@78000 {
reg = <0x78000 0x77000>;
pool;
};
};
pinctrl: pinctrl {

1
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-compact.dtsi
View file

@ -101,6 +101,7 @@
status = "okay";
};
&pwm9 {
pinctrl-names = "default";
pinctrl-0 = <&pwm9m2_pins>;

16
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
View file

@ -218,6 +218,22 @@
status = "okay";
};
&vdec0 {
status = "okay";
};
&vdec1 {
status = "okay";
};
&vdec0_sram {
status = "okay";
};
&vdec1_sram {
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;

41
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-1.dts
View file

@ -303,8 +303,8 @@
green_led@2 {
gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
label = "green_led";
linux,default-trigger = "heartbeat";
linux,default-trigger-delay-ms = <0>;
linux,default-trigger = "disk-activity";
//linux,default-trigger-delay-ms = <0>;
};
@ -338,29 +338,17 @@
status = "okay";
};
// &usbdp_phy0_dp {
// status = "okay";
// };
// &usbdp_phy0_u3 {
// status = "okay";
// };
&dp0 {
//pinctrl-0 = <&dp0m0_pins>;
pinctrl-0 = <&dp0m0_pins>;
pinctrl-names = "default";
hpd-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&dp0_hpd>;
status = "disabled";
};
&spdif_tx2{
//hpd-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
//pinctrl-0 = <&dp0_hpd>;
status = "okay";
};
&dp0_in {
dp0_in_vp1: endpoint {
remote-endpoint = <&vp1_out_dp0>;
@ -373,6 +361,10 @@
};
};
&spdif_tx2{
status = "okay";
};
// &dp0_out {
// };
@ -397,6 +389,10 @@
status = "okay";
};
&vdec1_sram {
status = "okay";
};
&vepu121_0 {
status = "okay";
};
@ -842,9 +838,9 @@
status = "okay";
};
&vpu121 {
status = "okay";
};
// &vpu121 {
// status = "okay";
// };
&vop {
status = "okay";
@ -1234,9 +1230,6 @@
status = "okay";
};
// &usb2phy0_grf {
// status = "okay";
// };
&usbdp_phy0 {
status = "okay";

238
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera1.dtsi Normal file
View file

@ -0,0 +1,238 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2025 Venkata Atchuta Bheemeswara Sarma Darbha
*
*/
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
&csi2_dphy0 {
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov13850_out2>;
data-lanes = <1 2>;
};
mipi_in_ucam1: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13855_out2>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
ov13855_1: ov13855-1@36 {
compatible = "ovti,ov13855";
status = "disabled";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim1_camera3_clk>;
reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2016-FV1";
rockchip,camera-module-lens-name = "default";
lens-focus = <&dw9714_p1>;
port {
ov13855_out2: endpoint {
remote-endpoint = <&csi2_input>;
data-lanes = <1 2>;
};
};
};
};
&mipi2_csi2 {
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&rkcif_mipi_lvds2 {
status = "disabled";
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "disabled";
port {
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp0_vir1>;
};
};
};
&rkisp0_vir1 {
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>;
};
};
};
// TODO- BSP to mainline conversion
&{/} {
vcc_cam0: vcc-cam0-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_power0_en>;
regulator-name = "vcc_cam0";
vin-supply = <&vcc_3v3_s3>;
};
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ov13855_1: ov13855-1@36 {
compatible = "ovti,ov13855";
status = "disabled";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim1_camera3_clk>;
reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2016-FV1";
rockchip,camera-module-lens-name = "default";
lens-focus = <&dw9714_p1>;
port {
ov13855_out2: endpoint {
remote-endpoint = <&csi2_input>;
data-lanes = <1 2>;
};
};
};
imx415: camera-sensor@1a {
compatible = "sony,imx415";
reg = <0x1a>;
assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
assigned-clock-rates = <27000000>;
avdd-supply = <&vcc_cam0>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "inck";
dvdd-supply = <&vcc_cam0>;
orientation = <2>; /* External */
ovdd-supply = <&vcc_cam0>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_rstn &mipim0_camera3_clk>;
reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
port {
imx415_ep: endpoint {
data-lanes = <1 2 3 4>;
link-frequencies = /bits/ 64 <445500000>;
remote-endpoint = <&csi2_input>;
};
};
};
};
&pinctrl {
cam0 {
cam0_power0_en: cam0-power0-en-pinctrl {
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
cam0_rstn: cam0-rstn-pinctrl {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&csi2 {
status = "okay";
};
&csi2_in {
csi2_input: endpoint {
data-lanes = <1 2 3 4>;
link-frequencies = /bits/ 64 <445500000>;
remote-endpoint = <&ov13855_out2>;
};
};
&csi_dphy0 {
status = "okay";
};
&vicap {
status = "okay";
};
&vicap_mmu0 {
status = "okay";
};
&vicap_mmu1 {
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
View file

@ -20,8 +20,8 @@
gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
regulator-name = "vcc3v3_pcie20";
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <50000>;
vin-supply = <&vcc5v0_sys>;
};

16
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi
View file

@ -198,6 +198,22 @@
};
};
&vdec0 {
status = "okay";
};
&vdec1 {
status = "okay";
};
&vdec0_sram {
status = "okay";
};
&vdec1_sram {
status = "okay";
};
&hdmi0_sound {
status = "okay";
};

14
arch/arm64/configs/android_orangepi5_defconfig
View file

@ -609,10 +609,10 @@ CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_FREQ_TIMES=y
#CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
#CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
@ -1022,6 +1022,8 @@ CONFIG_MEMFD_CREATE=y
CONFIG_ARCH_HAS_IOREMAP_PHYS_HOOKS=y
CONFIG_SECRETMEM=y
#CONFIG_ANON_VMA_NAME=y
CONFIG_HAVE_ARCH_USERFAULTFD_WP=y
CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y
CONFIG_USERFAULTFD=y
CONFIG_LRU_GEN=y
CONFIG_LRU_GEN_ENABLED=y
@ -3830,7 +3832,7 @@ CONFIG_TOUCHSCREEN_HIDEEP=m
CONFIG_TOUCHSCREEN_HYCON_HY46XX=m
# CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set
CONFIG_TOUCHSCREEN_ILI210X=m
CONFIG_TOUCHSCREEN_ILITEK=m
CONFIG_TOUCHSCREEN_ILITEK=y
CONFIG_TOUCHSCREEN_S6SY761=m
CONFIG_TOUCHSCREEN_GUNZE=m
CONFIG_TOUCHSCREEN_EKTF2127=m
@ -6940,7 +6942,7 @@ CONFIG_HID_MEGAWORLD_FF=m
CONFIG_HID_REDRAGON=m
CONFIG_HID_MICROSOFT=m
CONFIG_HID_MONTEREY=m
CONFIG_HID_MULTITOUCH=m
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NINTENDO=m
# CONFIG_NINTENDO_FF is not set
CONFIG_HID_NTI=m
@ -7381,7 +7383,7 @@ CONFIG_USB_G_WEBCAM=m
CONFIG_USB_RAW_GADGET=m
# end of USB Gadget precomposed configurations
CONFIG_TYPEC=m
CONFIG_TYPEC=y
CONFIG_TYPEC_TCPM=m
CONFIG_TYPEC_TCPCI=m
CONFIG_TYPEC_RT1711H=m
@ -9972,7 +9974,7 @@ CONFIG_DMA_CMA=y
#
# Default contiguous memory area size:
#
CONFIG_CMA_SIZE_MBYTES=512
CONFIG_CMA_SIZE_MBYTES=728
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SIZE_SEL_MIN is not set

7
drivers/gpu/drm/bridge/simple-bridge.c
View file

@ -278,6 +278,13 @@ static const struct of_device_id simple_bridge_match[] = {
.connector_type = DRM_MODE_CONNECTOR_VGA,
},
},
{
.compatible = "lontinum,lt8712",
.data = &(const struct simple_bridge_info) {
.connector_type = DRM_MODE_CONNECTOR_HDMIA,
},
},
{},
};
MODULE_DEVICE_TABLE(of, simple_bridge_match);

7
drivers/gpu/drm/bridge/synopsys/Kconfig
View file

@ -1,4 +1,11 @@
# SPDX-License-Identifier: GPL-2.0-only
config DRM_DW_DP
tristate
select DRM_DISPLAY_HELPER
select DRM_DISPLAY_DP_HELPER
select DRM_KMS_HELPER
select REGMAP_MMIO
config DRM_DW_HDMI
tristate
select DRM_DISPLAY_HDMI_HELPER

1
drivers/gpu/drm/bridge/synopsys/Makefile
View file

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_DRM_DW_DP) += dw-dp.o
obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
obj-$(CONFIG_DRM_DW_HDMI_GP_AUDIO) += dw-hdmi-gp-audio.o

2053
drivers/gpu/drm/bridge/synopsys/dw-dp.c Normal file
View file

File diff suppressed because it is too large Load diff

70
drivers/gpu/drm/display/drm_dp_helper.c
View file

@ -838,6 +838,76 @@ int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
/**
* drm_dp_link_power_up() - power up a DisplayPort link
* @aux: DisplayPort AUX channel
* @revision: DPCD revision supported on the link
*
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision)
{
u8 value;
int err;
/* DP_SET_POWER register is only available on DPCD v1.1 and later */
if (revision < DP_DPCD_REV_11)
return 0;
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
if (err < 0)
return err;
value &= ~DP_SET_POWER_MASK;
value |= DP_SET_POWER_D0;
err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
if (err < 0)
return err;
/*
* According to the DP 1.1 specification, a "Sink Device must exit the
* power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
* Control Field" (register 0x600).
*/
usleep_range(1000, 2000);
return 0;
}
EXPORT_SYMBOL(drm_dp_link_power_up);
/**
* drm_dp_link_power_down() - power down a DisplayPort link
* @aux: DisplayPort AUX channel
* @revision: DPCD revision supported on the link
*
* Returns 0 on success or a negative error code on failure.
*/
int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision)
{
u8 value;
int err;
/* DP_SET_POWER register is only available on DPCD v1.1 and later */
if (revision < DP_DPCD_REV_11)
return 0;
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
if (err < 0)
return err;
value &= ~DP_SET_POWER_MASK;
value |= DP_SET_POWER_D3;
err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
if (err < 0)
return err;
return 0;
}
EXPORT_SYMBOL(drm_dp_link_power_down);
static int read_payload_update_status(struct drm_dp_aux *aux)
{
int ret;

6
drivers/gpu/drm/rockchip/Kconfig
View file

@ -9,6 +9,7 @@ config DRM_ROCKCHIP
select VIDEOMODE_HELPERS
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
select DRM_DW_DP if ROCKCHIP_DW_DP
select DRM_DW_HDMI_QP if ROCKCHIP_DW_HDMI_QP
select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
select DRM_DW_MIPI_DSI2 if ROCKCHIP_DW_MIPI_DSI2
@ -57,6 +58,11 @@ config ROCKCHIP_CDN_DP
for the cdn DP driver. If you want to enable Dp on
RK3399 based SoC, you should select this
option.
config ROCKCHIP_DW_DP
bool "Rockchip specific extensions for Synopsys DW DP"
help
Choose this option for Synopsys DesignWare Cores DisplayPort
transmit controller support on Rockchip SoC.
config ROCKCHIP_DW_HDMI
bool "Rockchip specific extensions for Synopsys DW HDMI"

2
drivers/gpu/drm/rockchip/Makefile
View file

@ -14,9 +14,11 @@ rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI_QP) += dw_hdmi_qp-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI2) += dw-mipi-dsi2-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_DP) += dw_dp-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
rockchipdrm-$(CONFIG_ROCKCHIP_RGB) += rockchip_rgb.o
rockchipdrm-$(CONFIG_ROCKCHIP_RK3066_HDMI) += rk3066_hdmi.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o

154
drivers/gpu/drm/rockchip/dw_dp-rockchip.c Normal file
View file

@ -0,0 +1,154 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*
* Author: Zhang Yubing <yubing.zhang@rock-chips.com>
* Author: Andy Yan <andy.yan@rock-chips.com>
*/
#include <linux/component.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <drm/bridge/dw_dp.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_bridge_connector.h>
#include <drm/drm_of.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_simple_kms_helper.h>
#include <linux/media-bus-format.h>
#include <linux/videodev2.h>
#include "rockchip_drm_drv.h"
#include "rockchip_drm_vop.h"
struct rockchip_dw_dp {
struct dw_dp *base;
struct device *dev;
struct rockchip_encoder encoder;
};
static inline struct rockchip_dw_dp *encoder_to_dp(struct drm_encoder *encoder)
{
struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
return container_of(rkencoder, struct rockchip_dw_dp, encoder);
}
static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
struct drm_atomic_state *state = conn_state->state;
struct drm_display_info *di = &conn_state->connector->display_info;
struct drm_bridge *bridge = drm_bridge_chain_get_first_bridge(encoder);
struct drm_bridge_state *bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
u32 bus_format = bridge_state->input_bus_cfg.format;
switch (bus_format) {
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
break;
case MEDIA_BUS_FMT_YUYV10_1X20:
case MEDIA_BUS_FMT_YUYV8_1X16:
s->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY;
break;
case MEDIA_BUS_FMT_RGB101010_1X30:
case MEDIA_BUS_FMT_RGB888_1X24:
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
case MEDIA_BUS_FMT_YUV10_1X30:
case MEDIA_BUS_FMT_YUV8_1X24:
default:
s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
break;
}
s->output_type = DRM_MODE_CONNECTOR_DisplayPort;
s->bus_format = bus_format;
s->bus_flags = di->bus_flags;
s->color_space = V4L2_COLORSPACE_DEFAULT;
return 0;
}
static const struct drm_encoder_helper_funcs dw_dp_encoder_helper_funcs = {
.atomic_check = dw_dp_encoder_atomic_check,
};
static int dw_dp_rockchip_bind(struct device *dev, struct device *master, void *data)
{
struct dw_dp_plat_data plat_data;
struct drm_device *drm_dev = data;
struct rockchip_dw_dp *dp;
struct drm_encoder *encoder;
struct drm_connector *connector;
int ret;
dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
if (!dp)
return -ENOMEM;
dp->dev = dev;
plat_data.max_link_rate = 810000;
encoder = &dp->encoder.encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder, dev->of_node, 0, 0);
ret = drmm_encoder_init(drm_dev, encoder, NULL, DRM_MODE_ENCODER_TMDS, NULL);
if (ret)
return ret;
drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs);
dp->base = dw_dp_bind(dev, encoder, &plat_data);
if (IS_ERR(dp->base)) {
ret = PTR_ERR(dp->base);
return ret;
}
connector = drm_bridge_connector_init(drm_dev, encoder);
if (IS_ERR(connector)) {
ret = PTR_ERR(connector);
return dev_err_probe(dev, ret, "Failed to init bridge connector");
}
drm_connector_attach_encoder(connector, encoder);
return 0;
}
static const struct component_ops dw_dp_rockchip_component_ops = {
.bind = dw_dp_rockchip_bind,
};
static int dw_dp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
return component_add(dev, &dw_dp_rockchip_component_ops);
}
static void dw_dp_remove(struct platform_device *pdev)
{
struct rockchip_dw_dp *dp = platform_get_drvdata(pdev);
component_del(dp->dev, &dw_dp_rockchip_component_ops);
}
static const struct of_device_id dw_dp_of_match[] = {
{ .compatible = "rockchip,rk3588-dp", },
{}
};
MODULE_DEVICE_TABLE(of, dw_dp_of_match);
struct platform_driver dw_dp_driver = {
.probe = dw_dp_probe,
.remove = dw_dp_remove,
.driver = {
.name = "dw-dp",
.of_match_table = dw_dp_of_match,
},
};

1
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View file

@ -531,6 +531,7 @@ static int __init rockchip_drm_init(void)
ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
CONFIG_ROCKCHIP_ANALOGIX_DP);
ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP);
ADD_ROCKCHIP_SUB_DRIVER(dw_dp_driver, CONFIG_ROCKCHIP_DW_DP);
ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_rockchip_pltfm_driver,
CONFIG_ROCKCHIP_DW_HDMI);
ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_qp_rockchip_pltfm_driver,

1
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View file

@ -87,6 +87,7 @@ int rockchip_drm_encoder_set_crtc_endpoint_id(struct rockchip_encoder *rencoder,
struct device_node *np, int port, int reg);
int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
extern struct platform_driver cdn_dp_driver;
extern struct platform_driver dw_dp_driver;
extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
extern struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver;
extern struct platform_driver dw_mipi_dsi_rockchip_driver;

41
include/drm/bridge/dw_dp.h Normal file
View file

@ -0,0 +1,41 @@
// /* SPDX-License-Identifier: GPL-2.0-or-later */
// /*
// * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
// */
// #ifndef __DW_DP__
// #define __DW_DP__
// struct device;
// struct drm_encoder;
// struct dw_dp;
// struct dw_dp_plat_data {
// u32 max_link_rate;
// };
// struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
// const struct dw_dp_plat_data *plat_data);
// #endif /* __DW_DP__ */
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
*/
#ifndef __DW_DP__
#define __DW_DP__
#include <linux/device.h>
struct drm_encoder;
struct dw_dp;
struct dw_dp_plat_data {
u32 max_link_rate;
};
struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
const struct dw_dp_plat_data *plat_data);
#endif /* __DW_DP__ */

4
include/drm/display/drm_dp_helper.h
View file

@ -567,6 +567,10 @@ int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
enum drm_dp_phy dp_phy,
u8 link_status[DP_LINK_STATUS_SIZE]);
int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision);
int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision);
int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux,
int vcpid, u8 start_time_slot, u8 time_slot_count);
int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux);