lineage-rockchip/android_kernel_rockchip_tart
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Remove test files from tracking and add to gitignore

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dvab-sarma 2025-12-04 02:57:30 -06:00
parent 9a6c85c2de
commit 1ad8e7cb28
3 changed files with 2 additions and 346 deletions
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2
.gitignore vendored
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@ -181,3 +181,5 @@ sphinx_*/
# Rust analyzer configuration
/rust-project.json
arch/arm64/boot/dts/rockchip/overlays/orangepi-pro-cam1.dts
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera1.dtsi

108
arch/arm64/boot/dts/rockchip/overlays/orangepi-pro-cam1.dts
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@ -1,108 +0,0 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&csi2_dphy0_hw>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&csi2_dphy0>;
__overlay__ {
status = "okay";
};
};
fragment@2 {
target = <&mipi2_csi2>;
__overlay__ {
status = "okay";
};
};
fragment@3 {
target = <&rkcif_mipi_lvds2>;
__overlay__ {
status = "okay";
};
};
fragment@4 {
target = <&rkcif_mipi_lvds2_sditf>;
__overlay__ {
status = "okay";
};
};
fragment@5 {
target = <&rkisp0_vir1>;
__overlay__ {
status = "okay";
};
};
fragment@6 {
target = <&i2c7>;
__overlay__ {
status = "okay";
// vm149c-p1@c {
// status = "okay";
// };
// ov13850-1@10 {
// status = "okay";
// };
// dw9714-p1@c {
// status = "okay";
// };
ov13855-1@36 {
status = "okay";
};
};
};
fragment@7 {
target = <&rkcif>;
__overlay__ {
status = "okay";
};
};
fragment@8 {
target = <&rkcif_mmu>;
__overlay__ {
status = "okay";
};
};
fragment@9 {
target = <&rkisp0>;
__overlay__ {
status = "okay";
};
};
fragment@10 {
target = <&isp0_mmu>;
__overlay__ {
status = "okay";
};
};
};

238
arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro-camera1.dtsi
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@ -1,238 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* Copyright (c) 2025 Venkata Atchuta Bheemeswara Sarma Darbha
*
*/
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
&csi2_dphy0 {
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov13850_out2>;
data-lanes = <1 2>;
};
mipi_in_ucam1: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13855_out2>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
ov13855_1: ov13855-1@36 {
compatible = "ovti,ov13855";
status = "disabled";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim1_camera3_clk>;
reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2016-FV1";
rockchip,camera-module-lens-name = "default";
lens-focus = <&dw9714_p1>;
port {
ov13855_out2: endpoint {
remote-endpoint = <&csi2_input>;
data-lanes = <1 2>;
};
};
};
};
&mipi2_csi2 {
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&rkcif_mipi_lvds2 {
status = "disabled";
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "disabled";
port {
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp0_vir1>;
};
};
};
&rkisp0_vir1 {
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>;
};
};
};
// TODO- BSP to mainline conversion
&{/} {
vcc_cam0: vcc-cam0-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_power0_en>;
regulator-name = "vcc_cam0";
vin-supply = <&vcc_3v3_s3>;
};
};
&i2c3 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ov13855_1: ov13855-1@36 {
compatible = "ovti,ov13855";
status = "disabled";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim1_camera3_clk>;
reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2016-FV1";
rockchip,camera-module-lens-name = "default";
lens-focus = <&dw9714_p1>;
port {
ov13855_out2: endpoint {
remote-endpoint = <&csi2_input>;
data-lanes = <1 2>;
};
};
};
imx415: camera-sensor@1a {
compatible = "sony,imx415";
reg = <0x1a>;
assigned-clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
assigned-clock-rates = <27000000>;
avdd-supply = <&vcc_cam0>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "inck";
dvdd-supply = <&vcc_cam0>;
orientation = <2>; /* External */
ovdd-supply = <&vcc_cam0>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_rstn &mipim0_camera3_clk>;
reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
port {
imx415_ep: endpoint {
data-lanes = <1 2 3 4>;
link-frequencies = /bits/ 64 <445500000>;
remote-endpoint = <&csi2_input>;
};
};
};
};
&pinctrl {
cam0 {
cam0_power0_en: cam0-power0-en-pinctrl {
rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
cam0_rstn: cam0-rstn-pinctrl {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&csi2 {
status = "okay";
};
&csi2_in {
csi2_input: endpoint {
data-lanes = <1 2 3 4>;
link-frequencies = /bits/ 64 <445500000>;
remote-endpoint = <&ov13855_out2>;
};
};
&csi_dphy0 {
status = "okay";
};
&vicap {
status = "okay";
};
&vicap_mmu0 {
status = "okay";
};
&vicap_mmu1 {
status = "okay";
};