47e629b70d
Since some drivers (AMDGPU, Tegra) may have to do expensive tiling and detiling operations, we should try to take advantage of the access regions passed in by gralloc and gbm. Let's refactor struct map_data so we can separate the actual mapping and access region. Here is the Coccinelle rule used in this change: @@ struct map_info *M; @@ - (M) + M->vma In addition, struct map_data was also renamed to struct mapping. BUG=chromium:764871 TEST= mmap_test -g on Kevin Change-Id: Idb094aa3b5f81e45ce3a2f4fb2d9bf8fba32bf29 Reviewed-on: https://chromium-review.googlesource.com/758144 Commit-Ready: Gurchetan Singh <gurchetansingh@chromium.org> Tested-by: Gurchetan Singh <gurchetansingh@chromium.org> Reviewed-by: Joe Kniss <djmk@google.com> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/*
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* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifdef DRV_VC4
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#include <stdio.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <vc4_drm.h>
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#include <xf86drm.h>
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#include "drv_priv.h"
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#include "helpers.h"
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#include "util.h"
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static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
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DRM_FORMAT_XRGB8888 };
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static int vc4_init(struct driver *drv)
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{
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int ret;
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ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
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&LINEAR_METADATA, BO_USE_RENDER_MASK);
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if (ret)
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return ret;
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return drv_modify_linear_combinations(drv);
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}
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static int vc4_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
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uint64_t use_flags)
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{
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int ret;
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size_t plane;
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uint32_t stride;
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struct drm_vc4_create_bo bo_create;
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/*
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* Since the ARM L1 cache line size is 64 bytes, align to that as a
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* performance optimization.
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*/
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stride = drv_stride_from_format(format, width, 0);
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stride = ALIGN(stride, 64);
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drv_bo_from_format(bo, stride, height, format);
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memset(&bo_create, 0, sizeof(bo_create));
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bo_create.size = bo->total_size;
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ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VC4_CREATE_BO, &bo_create);
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if (ret) {
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fprintf(stderr, "drv: DRM_IOCTL_VC4_GEM_CREATE failed (size=%zu)\n",
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bo->total_size);
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return ret;
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}
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for (plane = 0; plane < bo->num_planes; plane++)
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bo->handles[plane].u32 = bo_create.handle;
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return 0;
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}
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static void *vc4_bo_map(struct bo *bo, struct mapping *mapping, size_t plane, uint32_t map_flags)
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{
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int ret;
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struct drm_vc4_mmap_bo bo_map;
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memset(&bo_map, 0, sizeof(bo_map));
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bo_map.handle = bo->handles[0].u32;
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ret = drmCommandWriteRead(bo->drv->fd, DRM_VC4_MMAP_BO, &bo_map, sizeof(bo_map));
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if (ret) {
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fprintf(stderr, "drv: DRM_VC4_MMAP_BO failed\n");
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return MAP_FAILED;
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}
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mapping->vma->length = bo->total_size;
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return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
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bo_map.offset);
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}
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const struct backend backend_vc4 = {
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.name = "vc4",
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.init = vc4_init,
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.bo_create = vc4_bo_create,
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.bo_import = drv_prime_bo_import,
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.bo_destroy = drv_gem_bo_destroy,
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.bo_map = vc4_bo_map,
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.bo_unmap = drv_bo_munmap,
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};
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#endif
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