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minigbm: i915: use experimental uapi

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New proposed i915 features for testing purposes.

BUG=b:153111783,b:155511259
TEST=Protected playback works w/ associated Chrome OS changes

Change-Id: I67bb178794d827c85667bff2fb4500c69fe0a4e3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/minigbm/+/2459531
Reviewed-by: Jeffrey Kardatzke <jkardatzke@google.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Jeffrey Kardatzke <jkardatzke@google.com>
Commit-Queue: Gurchetan Singh <gurchetansingh@chromium.org>
This commit is contained in:
Gurchetan Singh 2020-10-07 14:42:49 -07:00 • committed by Commit Bot
parent 13b0012204
commit f2bc3994e1
1 changed files with 727 additions and 41 deletions
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768
external/i915_drm.h vendored
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@ -24,8 +24,8 @@
*
*/
#ifndef _I915_DRM_H_
#define _I915_DRM_H_
#ifndef _UAPI_I915_DRM_H_
#define _UAPI_I915_DRM_H_
#include "drm.h"
@ -62,6 +62,28 @@ extern "C" {
#define I915_ERROR_UEVENT "ERROR"
#define I915_RESET_UEVENT "RESET"
/*
* i915_user_extension: Base class for defining a chain of extensions
*
* Many interfaces need to grow over time. In most cases we can simply
* extend the struct and have userspace pass in more data. Another option,
* as demonstrated by Vulkan's approach to providing extensions for forward
* and backward compatibility, is to use a list of optional structs to
* provide those extra details.
*
* The key advantage to using an extension chain is that it allows us to
* redefine the interface more easily than an ever growing struct of
* increasing complexity, and for large parts of that interface to be
* entirely optional. The downside is more pointer chasing; chasing across
* the __user boundary with pointers encapsulated inside u64.
*/
struct i915_user_extension {
__u64 next_extension;
__u32 name;
__u32 flags; /* All undefined bits must be zero. */
__u32 rsvd[4]; /* Reserved for future use; must be zero. */
};
/*
* MOCS indexes used for GPU surfaces, defining the cacheability of the
* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
@ -99,9 +121,25 @@ enum drm_i915_gem_engine_class {
I915_ENGINE_CLASS_VIDEO = 2,
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
/* should be kept compact */
I915_ENGINE_CLASS_INVALID = -1
};
/*
* There may be more than one engine fulfilling any role within the system.
* Each engine of a class is given a unique instance number and therefore
* any engine can be specified by its class:instance tuplet. APIs that allow
* access to any engine in the system will use struct i915_engine_class_instance
* for this identification.
*/
struct i915_engine_class_instance {
__u16 engine_class; /* see enum drm_i915_gem_engine_class */
__u16 engine_instance;
#define I915_ENGINE_CLASS_INVALID_NONE -1
#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
};
/**
* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
*
@ -319,6 +357,9 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_PERF_ADD_CONFIG 0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_I915_QUERY 0x39
#define DRM_I915_GEM_VM_CREATE 0x3a
#define DRM_I915_GEM_VM_DESTROY 0x3b
/* Must be kept compact -- no holes */
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@ -350,10 +391,12 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
@ -367,6 +410,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
@ -377,6 +421,8 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@ -412,6 +458,14 @@ typedef struct drm_i915_irq_wait {
int irq_seq;
} drm_i915_irq_wait_t;
/*
* Different modes of per-process Graphics Translation Table,
* see I915_PARAM_HAS_ALIASING_PPGTT
*/
#define I915_GEM_PPGTT_NONE 0
#define I915_GEM_PPGTT_ALIASING 1
#define I915_GEM_PPGTT_FULL 2
/* Ioctl to query kernel params:
*/
#define I915_PARAM_IRQ_ACTIVE 1
@ -468,6 +522,8 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
#define I915_PARAM_HUC_STATUS 42
@ -551,6 +607,21 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_MMAP_GTT_COHERENT 52
/*
* Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
* execution through use of explicit fence support.
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
*/
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
/*
* Revision of the i915-perf uAPI. The value returned helps determine what
* i915-perf features are available. See drm_i915_perf_property_id.
*/
#define I915_PARAM_PERF_REVISION 54
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
__s32 param;
/*
@ -566,6 +637,7 @@ typedef struct drm_i915_getparam {
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
#define I915_SETPARAM_NUM_USED_FENCES 4
/* Must be kept compact -- no holes */
typedef struct drm_i915_setparam {
int param;
@ -651,6 +723,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
struct drm_i915_gem_create_ext {
/**
* Requested size for the object.
*
* The (page-aligned) allocated size for the object will be returned.
*/
__u64 size;
/**
* Returned handle for the object.
*
* Object handles are nonzero.
*/
__u32 handle;
__u32 pad;
#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
(-(I915_GEM_CREATE_EXT_SETPARAM << 1))
__u64 extensions;
};
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@ -723,6 +816,37 @@ struct drm_i915_gem_mmap_gtt {
__u64 offset;
};
struct drm_i915_gem_mmap_offset {
/** Handle for the object being mapped. */
__u32 handle;
__u32 pad;
/**
* Fake offset to use for subsequent mmap call
*
* This is a fixed-size type for 32/64 compatibility.
*/
__u64 offset;
/**
* Flags for extended behaviour.
*
* It is mandatory that one of the MMAP_OFFSET types
* (GTT, WC, WB, UC, etc) should be included.
*/
__u64 flags;
#define I915_MMAP_OFFSET_GTT 0
#define I915_MMAP_OFFSET_WC 1
#define I915_MMAP_OFFSET_WB 2
#define I915_MMAP_OFFSET_UC 3
/*
* Zero-terminated chain of extensions.
*
* No current extensions defined; mbz.
*/
__u64 extensions;
};
struct drm_i915_gem_set_domain {
/** Handle for the object */
__u32 handle;
@ -964,7 +1088,7 @@ struct drm_i915_gem_execbuffer2 {
* struct drm_i915_gem_exec_fence *fences.
*/
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (7<<0)
#define I915_EXEC_RING_MASK (0x3f)
#define I915_EXEC_DEFAULT (0<<0)
#define I915_EXEC_RENDER (1<<0)
#define I915_EXEC_BSD (2<<0)
@ -1070,7 +1194,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_ARRAY (1<<19)
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))
/*
* Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
* a sync_file fd to wait upon (in a nonblocking manner) prior to executing
* the batch.
*
* Returns -EINVAL if the sync_file fd cannot be found.
*/
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
@ -1112,32 +1245,34 @@ struct drm_i915_gem_busy {
* as busy may become idle before the ioctl is completed.
*
* Furthermore, if the object is busy, which engine is busy is only
* provided as a guide. There are race conditions which prevent the
* report of which engines are busy from being always accurate.
* However, the converse is not true. If the object is idle, the
* result of the ioctl, that all engines are idle, is accurate.
* provided as a guide and only indirectly by reporting its class
* (there may be more than one engine in each class). There are race
* conditions which prevent the report of which engines are busy from
* being always accurate. However, the converse is not true. If the
* object is idle, the result of the ioctl, that all engines are idle,
* is accurate.
*
* The returned dword is split into two fields to indicate both
* the engines on which the object is being read, and the
* engine on which it is currently being written (if any).
* the engine classess on which the object is being read, and the
* engine class on which it is currently being written (if any).
*
* The low word (bits 0:15) indicate if the object is being written
* to by any engine (there can only be one, as the GEM implicit
* synchronisation rules force writes to be serialised). Only the
* engine for the last write is reported.
* engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
* 1 not 0 etc) for the last write is reported.
*
* The high word (bits 16:31) are a bitmask of which engines are
* currently reading from the object. Multiple engines may be
* The high word (bits 16:31) are a bitmask of which engines classes
* are currently reading from the object. Multiple engines may be
* reading from the object simultaneously.
*
* The value of each engine is the same as specified in the
* EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
* Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
* the I915_EXEC_RENDER engine for execution, and so it is never
* The value of each engine class is the same as specified in the
* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
* reported as active itself. Some hardware may have parallel
* execution engines, e.g. multiple media engines, which are
* mapped to the same identifier in the EXECBUFFER2 ioctl and
* so are not separately reported for busyness.
* mapped to the same class identifier and so are not separately
* reported for busyness.
*
* Caveat emptor:
* Only the boolean result of this query is reliable; that is whether
@ -1404,16 +1539,381 @@ struct drm_i915_gem_wait {
};
struct drm_i915_gem_context_create {
/* output: id of new context*/
__u32 ctx_id;
__u32 ctx_id; /* output: id of new context*/
__u32 pad;
};
struct drm_i915_gem_context_create_ext {
__u32 ctx_id; /* output: id of new context*/
__u32 flags;
#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
__u64 extensions;
};
struct drm_i915_gem_context_param {
__u32 ctx_id;
__u32 size;
__u64 param;
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
#define I915_CONTEXT_PARAM_BANNABLE 0x5
#define I915_CONTEXT_PARAM_PRIORITY 0x6
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
#define I915_CONTEXT_DEFAULT_PRIORITY 0
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
/*
* When using the following param, value should be a pointer to
* drm_i915_gem_context_param_sseu.
*/
#define I915_CONTEXT_PARAM_SSEU 0x7
/*
* Not all clients may want to attempt automatic recover of a context after
* a hang (for example, some clients may only submit very small incremental
* batches relying on known logical state of previous batches which will never
* recover correctly and each attempt will hang), and so would prefer that
* the context is forever banned instead.
*
* If set to false (0), after a reset, subsequent (and in flight) rendering
* from this context is discarded, and the client will need to create a new
* context to use instead.
*
* If set to true (1), the kernel will automatically attempt to recover the
* context by skipping the hanging batch and executing the next batch starting
* from the default context state (discarding the incomplete logical context
* state lost due to the reset).
*
* On creation, all new contexts are marked as recoverable.
*/
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
/*
* The id of the associated virtual memory address space (ppGTT) of
* this context. Can be retrieved and passed to another context
* (on the same fd) for both to use the same ppGTT and so share
* address layouts, and avoid reloading the page tables on context
* switches between themselves.
*
* See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
*/
#define I915_CONTEXT_PARAM_VM 0x9
/*
* I915_CONTEXT_PARAM_ENGINES:
*
* Bind this context to operate on this subset of available engines. Henceforth,
* the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
* an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
* and upwards. Slots 0...N are filled in using the specified (class, instance).
* Use
* engine_class: I915_ENGINE_CLASS_INVALID,
* engine_instance: I915_ENGINE_CLASS_INVALID_NONE
* to specify a gap in the array that can be filled in later, e.g. by a
* virtual engine used for load balancing.
*
* Setting the number of engines bound to the context to 0, by passing a zero
* sized argument, will revert back to default settings.
*
* See struct i915_context_param_engines.
*
* Extensions:
* i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
* i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
*/
#define I915_CONTEXT_PARAM_ENGINES 0xa
/*
* I915_CONTEXT_PARAM_PERSISTENCE:
*
* Allow the context and active rendering to survive the process until
* completion. Persistence allows fire-and-forget clients to queue up a
* bunch of work, hand the output over to a display server and then quit.
* If the context is marked as not persistent, upon closing (either via
* an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
* or process termination), the context and any outstanding requests will be
* cancelled (and exported fences for cancelled requests marked as -EIO).
*
* By default, new contexts allow persistence.
*/
#define I915_CONTEXT_PARAM_PERSISTENCE 0xb
/*
* I915_CONTEXT_PARAM_ACC:
*
* To be able to change the access counter thresholds and configurations.
*
* By default: access counter feature is disabled.
*/
#define I915_CONTEXT_PARAM_ACC 0xd
/*
* I915_CONTEXT_PARAM_PROTECTED_CONTENT:
*
* If set to true (1) PXP content protection is enabled.
* When enabled, the context is marked unrecoverable and may
* become invalid due to PXP teardown event or other error.
*/
#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xe
/* Must be kept compact -- no holes and well documented */
__u64 value;
};
struct drm_i915_gem_object_param {
/* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
__u32 handle;
/* Data pointer size */
__u32 size;
/*
* I915_OBJECT_PARAM:
*
* Select object namespace for the param.
*/
#define I915_OBJECT_PARAM (1ull<<32)
/*
* I915_PARAM_MEMORY_REGIONS:
*
* Set the data pointer with the desired set of placements in priority
* order(each entry must be unique and supported by the device), as an array of
* drm_i915_gem_memory_class_instance, or an equivalent layout of class:instance
* pair encodings. See DRM_I915_QUERY_MEMORY_REGIONS for how to query the
* supported regions.
*
* Note that this requires the I915_OBJECT_PARAM namespace:
* .param = I915_OBJECT_PARAM | I915_PARAM_MEMORY_REGIONS
*/
#define I915_PARAM_MEMORY_REGIONS 0x1
/*
* I915_PARAM_PROTECTED_CONTENT:
*
* If set to true (1) buffer contents is expected to be protected by
* PXP encryption and requires decryption for scan out and processing.
* Protected buffers can only be used in PXP protected contexts.
* A protected buffer may become invalid as a result of PXP teardown.
*/
#define I915_PARAM_PROTECTED_CONTENT 0x2
__u64 param;
/* Data value or pointer */
__u64 data;
};
struct drm_i915_gem_create_ext_setparam {
struct i915_user_extension base;
struct drm_i915_gem_object_param param;
};
/**
* Context SSEU programming
*
* It may be necessary for either functional or performance reason to configure
* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
* Sub-slice/EU).
*
* This is done by configuring SSEU configuration using the below
* @struct drm_i915_gem_context_param_sseu for every supported engine which
* userspace intends to use.
*
* Not all GPUs or engines support this functionality in which case an error
* code -ENODEV will be returned.
*
* Also, flexibility of possible SSEU configuration permutations varies between
* GPU generations and software imposed limitations. Requesting such a
* combination will return an error code of -EINVAL.
*
* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
* favour of a single global setting.
*/
struct drm_i915_gem_context_param_sseu {
/*
* Engine class & instance to be configured or queried.
*/
struct i915_engine_class_instance engine;
/*
* Unknown flags must be cleared to zero.
*/
__u32 flags;
#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
/*
* Mask of slices to enable for the context. Valid values are a subset
* of the bitmask value returned for I915_PARAM_SLICE_MASK.
*/
__u64 slice_mask;
/*
* Mask of subslices to enable for the context. Valid values are a
* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
*/
__u64 subslice_mask;
/*
* Minimum/Maximum number of EUs to enable per subslice for the
* context. min_eus_per_subslice must be inferior or equal to
* max_eus_per_subslice.
*/
__u16 min_eus_per_subslice;
__u16 max_eus_per_subslice;
/*
* Unused for now. Must be cleared to zero.
*/
__u32 rsvd;
};
/*
* i915_context_engines_load_balance:
*
* Enable load balancing across this set of engines.
*
* Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
* used will proxy the execbuffer request onto one of the set of engines
* in such a way as to distribute the load evenly across the set.
*
* The set of engines must be compatible (e.g. the same HW class) as they
* will share the same logical GPU context and ring.
*
* To intermix rendering with the virtual engine and direct rendering onto
* the backing engines (bypassing the load balancing proxy), the context must
* be defined to use a single timeline for all engines.
*/
struct i915_context_engines_load_balance {
struct i915_user_extension base;
__u16 engine_index;
__u16 num_siblings;
__u32 flags; /* all undefined flags must be zero */
__u64 mbz64; /* reserved for future use; must be zero */
struct i915_engine_class_instance engines[0];
} __attribute__((packed));
#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
struct i915_user_extension base; \
__u16 engine_index; \
__u16 num_siblings; \
__u32 flags; \
__u64 mbz64; \
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
/*
* i915_context_engines_bond:
*
* Constructed bonded pairs for execution within a virtual engine.
*
* All engines are equal, but some are more equal than others. Given
* the distribution of resources in the HW, it may be preferable to run
* a request on a given subset of engines in parallel to a request on a
* specific engine. We enable this selection of engines within a virtual
* engine by specifying bonding pairs, for any given master engine we will
* only execute on one of the corresponding siblings within the virtual engine.
*
* To execute a request in parallel on the master engine and a sibling requires
* coordination with a I915_EXEC_FENCE_SUBMIT.
*/
struct i915_context_engines_bond {
struct i915_user_extension base;
struct i915_engine_class_instance master;
__u16 virtual_index; /* index of virtual engine in ctx->engines[] */
__u16 num_bonds;
__u64 flags; /* all undefined flags must be zero */
__u64 mbz64[4]; /* reserved for future use; must be zero */
struct i915_engine_class_instance engines[0];
} __attribute__((packed));
#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
struct i915_user_extension base; \
struct i915_engine_class_instance master; \
__u16 virtual_index; \
__u16 num_bonds; \
__u64 flags; \
__u64 mbz64[4]; \
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
struct i915_engine_class_instance engines[0];
} __attribute__((packed));
#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
__u64 extensions; \
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
struct drm_i915_gem_context_create_ext_setparam {
#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
struct i915_user_extension base;
struct drm_i915_gem_context_param param;
};
struct drm_i915_gem_context_create_ext_clone {
#define I915_CONTEXT_CREATE_EXT_CLONE 1
struct i915_user_extension base;
__u32 clone_id;
__u32 flags;
#define I915_CONTEXT_CLONE_ENGINES (1u << 0)
#define I915_CONTEXT_CLONE_FLAGS (1u << 1)
#define I915_CONTEXT_CLONE_SCHEDATTR (1u << 2)
#define I915_CONTEXT_CLONE_SSEU (1u << 3)
#define I915_CONTEXT_CLONE_TIMELINE (1u << 4)
#define I915_CONTEXT_CLONE_VM (1u << 5)
#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)
__u64 rsvd;
};
struct drm_i915_gem_context_destroy {
__u32 ctx_id;
__u32 pad;
};
/*
* DRM_I915_GEM_VM_CREATE -
*
* Create a new virtual memory address space (ppGTT) for use within a context
* on the same file. Extensions can be provided to configure exactly how the
* address space is setup upon creation.
*
* The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
* returned in the outparam @id.
*
* No flags are defined, with all bits reserved and must be zero.
*
* An extension chain maybe provided, starting with @extensions, and terminated
* by the @next_extension being 0. Currently, no extensions are defined.
*
* DRM_I915_GEM_VM_DESTROY -
*
* Destroys a previously created VM id, specified in @id.
*
* No extensions or flags are allowed currently, and so must be zero.
*/
struct drm_i915_gem_vm_control {
__u64 extensions;
__u32 flags;
__u32 vm_id;
};
struct drm_i915_reg_read {
/*
* Register offset.
@ -1426,6 +1926,7 @@ struct drm_i915_reg_read {
__u64 val; /* Return value */
};
/* Known registers:
*
* Render engine timestamp - 0x2358 + 64bit - gen7+
@ -1465,22 +1966,6 @@ struct drm_i915_gem_userptr {
__u32 handle;
};
struct drm_i915_gem_context_param {
__u32 ctx_id;
__u32 size;
__u64 param;
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
#define I915_CONTEXT_PARAM_BANNABLE 0x5
#define I915_CONTEXT_PARAM_PRIORITY 0x6
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
#define I915_CONTEXT_DEFAULT_PRIORITY 0
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
__u64 value;
};
enum drm_i915_oa_format {
I915_OA_FORMAT_A13 = 1, /* HSW only */
I915_OA_FORMAT_A29, /* HSW only */
@ -1503,23 +1988,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
*
* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
*
* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
*
* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
*
* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@ -1529,9 +2022,22 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
*
* This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
/**
* Specifying this property is only valid when specify a context to
* filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
* will hold preemption of the particular context we want to gather
* performance data about. The execbuf2 submissions must include a
* drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
*
* This property is available in perf revision 3.
*/
DRM_I915_PERF_PROP_HOLD_PREEMPTION,
DRM_I915_PERF_PROP_MAX /* non-ABI */
};
@ -1560,6 +2066,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
*
* This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@ -1567,9 +2075,24 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
*
* This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
/**
* Change metrics_set captured by a stream.
*
* If the stream is bound to a specific context, the configuration change
* will performed inline with that context such that it takes effect before
* the next execbuf submission.
*
* Returns the previously bound metrics set id, or a negative error code.
*
* This ioctl is available in perf revision 2.
*/
#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
/**
* Common to all i915 perf records
*/
@ -1642,6 +2165,10 @@ struct drm_i915_perf_oa_config {
struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
#define DRM_I915_QUERY_PERF_CONFIG 3
#define DRM_I915_QUERY_MEMORY_REGIONS 4
/* Must be kept compact -- no holes and well documented */
/*
* When set to zero by userspace, this is filled with the size of the
@ -1652,9 +2179,18 @@ struct drm_i915_query_item {
__s32 length;
/*
* Unused for now. Must be cleared to zero.
* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
*
* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
* following :
* - DRM_I915_QUERY_PERF_CONFIG_LIST
* - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
* - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
*/
__u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
/*
* Data will be written at the location pointed by data_ptr when the
@ -1690,8 +2226,10 @@ struct drm_i915_query {
* (data[X / 8] >> (X % 8)) & 1
*
* - the subslice mask for each slice with one bit per subslice telling
* whether a subslice is available. The availability of subslice Y in slice
* X can be queried with the following formula :
* whether a subslice is available. Gen12 has dual-subslices, which are
* similar to two gen11 subslices. For gen12, this array represents dual-
* subslices. The availability of subslice Y in slice X can be queried
* with the following formula :
*
* (data[subslice_offset +
* X * subslice_stride +
@ -1739,8 +2277,156 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
/**
* struct drm_i915_engine_info
*
* Describes one engine and it's capabilities as known to the driver.
*/
struct drm_i915_engine_info {
/** Engine class and instance. */
struct i915_engine_class_instance engine;
/** Reserved field. */
__u32 rsvd0;
/** Engine flags. */
__u64 flags;
/** Capabilities of this engine. */
__u64 capabilities;
#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
/** Reserved fields. */
__u64 rsvd1[4];
};
/**
* struct drm_i915_query_engine_info
*
* Engine info query enumerates all engines known to the driver by filling in
* an array of struct drm_i915_engine_info structures.
*/
struct drm_i915_query_engine_info {
/** Number of struct drm_i915_engine_info structs following. */
__u32 num_engines;
/** MBZ */
__u32 rsvd[3];
/** Marker for drm_i915_engine_info structures. */
struct drm_i915_engine_info engines[];
};
/*
* Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
*/
struct drm_i915_query_perf_config {
union {
/*
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
* this fields to the number of configurations available.
*/
__u64 n_configs;
/*
* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
* i915 will use the value in this field as configuration
* identifier to decide what data to write into config_ptr.
*/
__u64 config;
/*
* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
* i915 will use the value in this field as configuration
* identifier to decide what data to write into config_ptr.
*
* String formatted like "%08x-%04x-%04x-%04x-%012x"
*/
char uuid[36];
};
/*
* Unused for now. Must be cleared to zero.
*/
__u32 flags;
/*
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
* write an array of __u64 of configuration identifiers.
*
* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
* write a struct drm_i915_perf_oa_config. If the following fields of
* drm_i915_perf_oa_config are set not set to 0, i915 will write into
* the associated pointers the values of submitted when the
* configuration was created :
*
* - n_mux_regs
* - n_boolean_regs
* - n_flex_regs
*/
__u8 data[];
};
enum drm_i915_gem_memory_class {
I915_MEMORY_CLASS_SYSTEM = 0,
I915_MEMORY_CLASS_DEVICE,
I915_MEMORY_CLASS_STOLEN_SYSTEM,
I915_MEMORY_CLASS_STOLEN_DEVICE,
};
struct drm_i915_gem_memory_class_instance {
__u16 memory_class; /* see enum drm_i915_gem_memory_class */
__u16 memory_instance;
};
/**
* struct drm_i915_memory_region_info
*
* Describes one region as known to the driver.
*/
struct drm_i915_memory_region_info {
/** class:instance pair encoding */
struct drm_i915_gem_memory_class_instance region;
/** MBZ */
__u32 rsvd0;
/** MBZ */
__u64 caps;
/** MBZ */
__u64 flags;
/** Memory probed by the driver (-1 = unknown) */
__u64 probed_size;
/** Estimate of memory remaining (-1 = unknown) */
__u64 unallocated_size;
/** MBZ */
__u64 rsvd1[8];
};
/**
* struct drm_i915_query_memory_regions
*
* Region info query enumerates all regions known to the driver by filling in
* an array of struct drm_i915_memory_region_info structures.
*/
struct drm_i915_query_memory_regions {
/** Number of supported regions */
__u32 num_regions;
/** MBZ */
__u32 rsvd[3];
/* Info about each supported region */
struct drm_i915_memory_region_info regions[];
};
#if defined(__cplusplus)
}
#endif
#endif /* _I915_DRM_H_ */
#endif /* _UAPI_I915_DRM_H_ */