mediatek.c: Don't use 64-stride alignment for video on 8173 (hana)
Video buffers are forced to use 64 alignment because of some nebulous argument around better cache performance (b/35560932, it was mostly about kevin and somehow hana got bundled in). On Mediatek, however, video decoder and image processor use 16- alignment (like macroblocks), forcing the use of the image processor to reconcile these two, negating any performance/cache improvements. This CL changes that to only use 64-alignment to non-YUV (hence, video) quads, and this only for Hana. BUG=b:220175010 TEST=video.DecodeAccel.* on hana Change-Id: I48ee1beac29f915734830eda64705a2b4827a901 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/minigbm/+/3475099 Tested-by: Miguel Casas-Sanchez <mcasas@chromium.org> Tested-by: Miguel Casas <mcasas@google.com> Reviewed-by: Fei Shao <fshao@chromium.org> Reviewed-by: Miguel Casas <mcasas@google.com> Commit-Queue: Miguel Casas <mcasas@google.com>
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1 changed files with 29 additions and 1 deletions
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mediatek.c
30
mediatek.c
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@ -32,6 +32,8 @@
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// All platforms except MT8173 should USE_NV12_FOR_HW_VIDEO_DECODING.
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#if defined(MTK_MT8183) || defined(MTK_MT8186) || defined(MTK_MT8192) || defined(MTK_MT8195)
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#define USE_NV12_FOR_HW_VIDEO_DECODING
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#else
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#define DONT_USE_64_ALIGNMENT_FOR_VIDEO_BUFFERS
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#endif
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struct mediatek_private_map_data {
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@ -56,8 +58,27 @@ static const uint32_t texture_source_formats[] = {
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DRM_FORMAT_YVU420,
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DRM_FORMAT_YVU420_ANDROID
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};
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#ifdef DONT_USE_64_ALIGNMENT_FOR_VIDEO_BUFFERS
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static const uint32_t video_yuv_formats[] = {
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DRM_FORMAT_NV21,
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DRM_FORMAT_NV12,
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DRM_FORMAT_YVU420,
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DRM_FORMAT_YVU420_ANDROID
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};
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// clang-format on
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static bool is_video_yuv_format(uint32_t format)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(video_yuv_formats); ++i) {
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if (format == video_yuv_formats[i])
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return true;
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}
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return false;
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}
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#endif
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static int mediatek_init(struct driver *drv)
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{
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struct format_metadata metadata;
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@ -130,10 +151,17 @@ static int mediatek_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint
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/*
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* Since the ARM L1 cache line size is 64 bytes, align to that as a
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* performance optimization.
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* performance optimization, except for video buffers on certain platforms,
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* these should only be accessed from the GPU and VCODEC subsystems (maybe
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* also MDP), so it's better to align to macroblocks.
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*/
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stride = drv_stride_from_format(format, width, 0);
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#ifdef DONT_USE_64_ALIGNMENT_FOR_VIDEO_BUFFERS
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const uint32_t alignment = is_video_yuv_format(format) ? 16 : 64;
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stride = ALIGN(stride, alignment);
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#else
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stride = ALIGN(stride, 64);
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#endif
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if (bo->meta.use_flags & BO_USE_HW_VIDEO_ENCODER) {
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uint32_t aligned_height = ALIGN(height, 32);
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