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anv: avoid storing L3 config on the pipeline

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On Gfx9 we only use 2 L3 config depending on SLM use or not. So it's
the same config for all Gfx pipelines.

On Gfx11+ there is only one config (since SLM is allocated from
somewhere else).

So avoid store this on the pipeline, pick the config when flushing the
pipeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36512>
This commit is contained in:
Lionel Landwerlin 2025-02-12 12:23:16 +02:00 • committed by Marge Bot
parent 240482f5f5
commit 99016a893a
7 changed files with 24 additions and 43 deletions
Download patch file Download diff file Expand all files Collapse all files

23
src/intel/vulkan/anv_pipeline.c
View file

@ -30,7 +30,6 @@
#include "util/mesa-sha1.h"
#include "util/os_time.h"
#include "common/intel_compute_slm.h"
#include "common/intel_l3_config.h"
#include "common/intel_sample_positions.h"
#include "compiler/brw_disasm.h"
#include "anv_private.h"
@ -2856,24 +2855,6 @@ VkResult anv_CreateComputePipelines(
return result;
}
/**
* Calculate the desired L3 partitioning based on the current state of the
* pipeline. For now this simply returns the conservative defaults calculated
* by get_default_l3_weights(), but we could probably do better by gathering
* more statistics from the pipeline state (e.g. guess of expected URB usage
* and bound surfaces), or by using feed-back from performance counters.
*/
void
anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
{
const struct intel_device_info *devinfo = pipeline->device->info;
const struct intel_l3_weights w =
intel_get_default_l3_weights(devinfo, true, needs_slm);
pipeline->l3_config = intel_get_l3_config(devinfo, w);
}
static uint32_t
get_vs_input_elements(const struct brw_vs_prog_data *vs_prog_data)
{
@ -2895,8 +2876,6 @@ anv_graphics_pipeline_emit(struct anv_graphics_pipeline *pipeline,
{
pipeline->view_mask = state->rp->view_mask;
anv_pipeline_setup_l3_config(&pipeline->base.base, false);
if (anv_pipeline_is_primitive(pipeline)) {
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
@ -4087,8 +4066,6 @@ anv_ray_tracing_pipeline_init(struct anv_ray_tracing_pipeline *pipeline,
ANV_FROM_HANDLE(vk_pipeline_layout, pipeline_layout, pCreateInfo->layout);
anv_pipeline_init_layout(&pipeline->base, pipeline_layout);
anv_pipeline_setup_l3_config(&pipeline->base, /* needs_slm */ false);
}
static void

6
src/intel/vulkan/anv_private.h
View file

@ -2128,6 +2128,7 @@ struct anv_device {
struct intel_aux_map_context *aux_map_ctx;
const struct intel_l3_config *l3_config;
const struct intel_l3_config *l3_slm_config;
struct intel_debug_block_frame *debug_frame_desc;
@ -4938,8 +4939,6 @@ struct anv_pipeline {
struct anv_pipeline_sets_layout layout;
struct util_dynarray executables;
const struct intel_l3_config * l3_config;
};
/* The base graphics pipeline object only hold shaders. */
@ -5497,9 +5496,6 @@ anv_swizzle_for_render(struct isl_swizzle swizzle)
return swizzle;
}
void
anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm);
/**
* Describes how each part of anv_image will be bound to memory.
*/

7
src/intel/vulkan/genX_cmd_compute.c
View file

@ -102,6 +102,7 @@ genX(cmd_buffer_ensure_cfe_state)(struct anv_cmd_buffer *cmd_buffer,
static void
cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
struct anv_cmd_compute_state *comp_state = &cmd_buffer->state.compute;
struct anv_compute_pipeline *pipeline =
anv_pipeline_to_compute(comp_state->base.pipeline);
@ -109,7 +110,9 @@ cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer)
assert(pipeline->cs);
genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->base.l3_config);
genX(cmd_buffer_config_l3)(cmd_buffer,
pipeline->cs->prog_data->total_shared > 0 ?
device->l3_slm_config : device->l3_config);
genX(cmd_buffer_update_color_aux_op(cmd_buffer, ISL_AUX_OP_NONE));
@ -1175,7 +1178,7 @@ cmd_buffer_trace_rays(struct anv_cmd_buffer *cmd_buffer,
trace_intel_begin_rays(&cmd_buffer->trace);
genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->base.l3_config);
genX(cmd_buffer_config_l3)(cmd_buffer, device->l3_config);
genX(cmd_buffer_update_color_aux_op(cmd_buffer, ISL_AUX_OP_NONE));

12
src/intel/vulkan/genX_cmd_draw.c
View file

@ -751,14 +751,16 @@ cmd_buffer_flush_vertex_buffers(struct anv_cmd_buffer *cmd_buffer,
ALWAYS_INLINE static void
cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_device *device = cmd_buffer->device;
const struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
struct anv_graphics_pipeline *pipeline =
anv_pipeline_to_graphics(cmd_buffer->state.gfx.base.pipeline);
anv_pipeline_to_graphics(gfx->base.pipeline);
const struct vk_dynamic_graphics_state *dyn =
&cmd_buffer->vk.dynamic_graphics_state;
assert((pipeline->base.base.active_stages & VK_SHADER_STAGE_COMPUTE_BIT) == 0);
genX(cmd_buffer_config_l3)(cmd_buffer, pipeline->base.base.l3_config);
genX(cmd_buffer_config_l3)(cmd_buffer, device->l3_config);
genX(cmd_buffer_update_color_aux_op(cmd_buffer, ISL_AUX_OP_NONE));
@ -830,7 +832,7 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
* 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_*
* state is not combined with other state changes.
*/
if (intel_needs_workaround(cmd_buffer->device->info, 16011411144)) {
if (intel_needs_workaround(device->info, 16011411144)) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_CS_STALL_BIT,
"before SO_BUFFER change WA");
@ -859,12 +861,12 @@ cmd_buffer_flush_gfx_state(struct anv_cmd_buffer *cmd_buffer)
/* Size is in DWords - 1 */
sob.SurfaceSize = DIV_ROUND_UP(xfb->size, 4) - 1;
} else {
sob.MOCS = anv_mocs(cmd_buffer->device, NULL, 0);
sob.MOCS = anv_mocs(device, NULL, 0);
}
}
}
if (intel_needs_workaround(cmd_buffer->device->info, 16011411144)) {
if (intel_needs_workaround(device->info, 16011411144)) {
/* Wa_16011411144: also CS_STALL after touching SO_BUFFER change */
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_CS_STALL_BIT,

2
src/intel/vulkan/genX_gfx_state.c
View file

@ -2085,7 +2085,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
#if GFX_VERx10 == 125
if ((gfx->dirty & ANV_CMD_DIRTY_RENDER_TARGETS))
update_tbimr_info(hw_state, device, gfx, pipeline->base.base.l3_config);
update_tbimr_info(hw_state, device, gfx, device->l3_config);
#endif
#if INTEL_WA_14018283232_GFX_VER

9
src/intel/vulkan/genX_init_state.c
View file

@ -200,7 +200,14 @@ init_common_queue_state(struct anv_queue *queue, struct anv_batch *batch)
*/
const struct intel_l3_config *cfg = intel_get_default_l3_config(device->info);
genX(emit_l3_config)(batch, device, cfg);
device->l3_config = cfg;
device->l3_config = device->l3_slm_config = cfg;
#else
device->l3_config = intel_get_l3_config(
device->info,
intel_get_default_l3_weights(device->info, true, false /* slm */));
device->l3_slm_config = intel_get_l3_config(
device->info,
intel_get_default_l3_weights(device->info, true, true /* slm */));
#endif
#if GFX_VERx10 == 125

8
src/intel/vulkan/genX_pipeline.c
View file

@ -530,7 +530,7 @@ emit_urb_setup_mesh(struct anv_graphics_pipeline *pipeline,
const struct brw_mesh_prog_data *mesh_prog_data = get_mesh_prog_data(pipeline);
const struct intel_mesh_urb_allocation alloc =
intel_get_mesh_urb_config(devinfo, pipeline->base.base.l3_config,
intel_get_mesh_urb_config(devinfo, pipeline->base.base.device->l3_config,
task_prog_data ? task_prog_data->map.size_dw : 0,
mesh_prog_data->map.size / 4);
@ -593,7 +593,7 @@ emit_urb_setup(struct anv_graphics_pipeline *pipeline,
bool constrained;
intel_get_urb_config(devinfo,
pipeline->base.base.l3_config,
pipeline->base.base.device->l3_config,
pipeline->base.base.active_stages &
VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
pipeline->base.base.active_stages &
@ -2043,8 +2043,6 @@ void
genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
{
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
anv_pipeline_setup_l3_config(&pipeline->base, prog_data->base.total_shared > 0);
const struct intel_device_info *devinfo = pipeline->base.device->info;
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
@ -2104,8 +2102,6 @@ genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
const struct intel_device_info *devinfo = device->info;
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
anv_pipeline_setup_l3_config(&pipeline->base, cs_prog_data->base.total_shared > 0);
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
const uint32_t vfe_curbe_allocation =