diff --git a/src/panfrost/lib/pan_props.c b/src/panfrost/lib/pan_props.c
index 4f9e070bda7..3beee592f55 100644
--- a/src/panfrost/lib/pan_props.c
+++ b/src/panfrost/lib/pan_props.c
@@ -75,6 +75,13 @@
       .z_size = z_tb_size,                                                     \
    }
 
+#define MODEL_RATES(pixel_rate, texel_rate, fma_rate)                          \
+   .rates = {                                                                  \
+      .pixel = pixel_rate,                                                     \
+      .texel = texel_rate,                                                     \
+      .fma = fma_rate,                                                         \
+   }
+
 #define MODEL_QUIRKS(...) .quirks = {__VA_ARGS__}
 
 /* Table of supported Mali GPUs */
@@ -101,17 +108,27 @@ const struct pan_model pan_model_list[] = {
    BIFROST_MODEL(0x7202,    "G52",    "TGOx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192)),
    BIFROST_MODEL(0x7402,    "G52 r1", "TGOx", MODEL_ANISO(ALL),  MODEL_TB_SIZES( 8192,  8192)),
 
-   VALHALL_MODEL(0x9001, 0, "G57",    "TNAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192)),
-   VALHALL_MODEL(0x9003, 0, "G57",    "TNAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192)),
-   VALHALL_MODEL(0xa807, 0, "G610",   "TVIx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(32768, 16384)),
-   VALHALL_MODEL(0xac04, 0, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192)),
-   VALHALL_MODEL(0xac04, 1, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192)),
-   VALHALL_MODEL(0xac04, 2, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192)),
-   VALHALL_MODEL(0xac04, 3, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(32768, 16384)),
-   VALHALL_MODEL(0xac04, 4, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(32768, 16384)),
+   VALHALL_MODEL(0x9001, 0, "G57",    "TNAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192),
+                                              MODEL_RATES(2, 4,  32)),
+   VALHALL_MODEL(0x9003, 0, "G57",    "TNAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192),
+                                              MODEL_RATES(2, 4,  32)),
+   VALHALL_MODEL(0xa807, 0, "G610",   "TVIx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(32768, 16384),
+                                              MODEL_RATES(4, 8,  64)),
+   VALHALL_MODEL(0xac04, 0, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192),
+                                              MODEL_RATES(2, 2,  16)),
+   VALHALL_MODEL(0xac04, 1, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192),
+                                              MODEL_RATES(2, 4,  32)),
+   VALHALL_MODEL(0xac04, 2, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(16384,  8192),
+                                              MODEL_RATES(4, 4,  48)),
+   VALHALL_MODEL(0xac04, 3, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(32768, 16384),
+                                              MODEL_RATES(4, 8,  48)),
+   VALHALL_MODEL(0xac04, 4, "G310",   "TVAx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(32768, 16384),
+                                              MODEL_RATES(4, 8,  64)),
 
-   AVALON_MODEL( 0xc800, 4, "G720",   "TTIx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(65536, 32768)),
-   AVALON_MODEL( 0xd800, 4, "G725",   "TKRx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(65536, 65536)),
+   AVALON_MODEL( 0xc800, 4, "G720",   "TTIx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(65536, 32768),
+                                              MODEL_RATES(4, 8, 128)),
+   AVALON_MODEL( 0xd800, 4, "G725",   "TKRx", MODEL_ANISO(ALL),  MODEL_TB_SIZES(65536, 65536),
+                                              MODEL_RATES(4, 8, 128)),
 };
 /* clang-format on */
 
@@ -129,6 +146,7 @@ const struct pan_model pan_model_list[] = {
 
 #undef MODEL_ANISO
 #undef MODEL_TB_SIZES
+#undef MODEL_RATES
 #undef MODEL_QUIRKS
 
 /*
diff --git a/src/panfrost/lib/pan_props.h b/src/panfrost/lib/pan_props.h
index b7c682bfc86..51c4218dcf5 100644
--- a/src/panfrost/lib/pan_props.h
+++ b/src/panfrost/lib/pan_props.h
@@ -84,6 +84,14 @@ struct pan_model {
       uint32_t z_size;
    } tilebuffer;
 
+   /* Maximum number of pixels, texels, and FMA ops, per clock per shader
+    * core, or 0 if it can't be determined for the given GPU. */
+   struct {
+      uint32_t pixel;
+      uint32_t texel;
+      uint32_t fma;
+   } rates;
+
    struct {
       /* The GPU lacks the capability for hierarchical tiling, without
        * an "Advanced Tiling Unit", instead requiring a single bin