lineage-rockchip/android_external_mesa3d
1
0
Fork 0
Code Activity Actions

ac, radeonsi: prepare cs_preamble_state for userq reg shadowing

Browse source 
register shadowing has to be enabled in CONTEXT_CONTROL packet
in cs_preamble_state for user queue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
This commit is contained in:
Yogesh Mohan Marimuthu 2025-06-16 14:43:13 +05:30 • committed by Marge Bot
parent aab890644b
commit 0186977988
4 changed files with 32 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

4
docs/envvars.rst
View file

@ -1744,6 +1744,10 @@ RadeonSI driver environment variables
Enable DPBB. Enable DPBB for gfx9 dGPU. Default enabled for gfx9 APU and >= gfx10.
``extra_md``
add extra information in bo metadata to help tools (umr)
``shadowregs``
Enable CP register shadowing in kernel queue.
``userqnoshadowregs``
Disable register shadowing in userqueue. This will also disable userqueue mcbp.
r600 driver environment variables
---------------------------------